Honored Contributor
Honored ContributorI perused the automatTest.vhd file. It truly is a large state machine. I saw 71555 states. If you'd take the approach I suggested earlier you would need more memory bits that you could find in any FPGA: about (2^(17+8) )* 20 = 671 Mbit.
So let's 'divide and conquer': most of the states are simple 'pass to next / jump on fail', a limited number of states have multiple jump targets so you could try to divide the decision-making over several RAM-lookup machines. This would limit the RAM-usage to about (2^17) * 27 = 3.6 Mbit I kind of like Kaz' idea to build a dedicated sequencer. It will have the advantage of being reasonably general (-> easy to change the state sequence etc.) but it will/can only examine one 'stream' condition per clock, unless you add separate 'stream' comparison blocks for the few 'multiple jump' cases which brings you back to the 'divide and conquer' approach. Being curious: what is the goal of this project?
