Honored Contributor
Honored ContributorHi,
due to this long compilation if it was me, I will go for memory based design i.e. design a dedicated processor in effect. Your memory can be as wide as you need. The address first points to count 0 (or state 0). The content of the location will encode information e.g. 16 bits for next count, bits for actions. Decide how many actions you have, design rtl only for them to be enabled accordingly. add wait states to your address...so on. So much of the logic is precomputed and stored, relieving the burden on logic of FPGA. You will need mif or hex file. the easiest way is to go quartus,files => new => mif => decide width and size then put few values, save. then look at it in an editor to see its format and then you can use any programming tool to generate the mif file for your data. I had posted recently a Matlab based approach to generate mif: http://www.alteraforum.com/forum/showthread.php?t=23628
