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JTUCK3's avatar
JTUCK3
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7 years ago

Problem simulating Verilog ip catalog uart with my VHDL design using Modelsim Altera starter edition

The IP catalog seems to generate Verilog, even though I ask for VHDL. It appears to create a top level VHDL wrapper for its Verilog design. As I'm using VHDL for my design, I get a simulation error "...
JTUCK3's avatar
JTUCK3
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7 years ago

Thanks Abraham, that would be my guess.

I was also questioning why the IP catalog can't generate its IP in VHDL. The Parameter Editor has a tick box - Verilog or VHDL - but that's not actually what it does.