Forum Discussion
JTUCK3
New Contributor
New ContributorProblem simulating Verilog ip catalog uart with my VHDL design using Modelsim Altera starter edition
The IP catalog seems to generate Verilog, even though I ask for VHDL. It appears to create a top level VHDL wrapper for its Verilog design. As I'm using VHDL for my design, I get a simulation error "...
JTUCK3New Contributor
New ContributorThanks Abraham, that would be my guess.
I was also questioning why the IP catalog can't generate its IP in VHDL. The Parameter Editor has a tick box - Verilog or VHDL - but that's not actually what it does.
