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Altera_Forum
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16 years ago

Problem rebuilding source with new Quartus II

Hello,

I recently inherited a project board which has a Stratix II EP2S30F672 FPGA which is booted from an EPC4QC100.

Project originally compiled under quartus vers 7. Now when the project is compiled under quartus vers 9 it compiles without error but will no longer run on target board. I am using the original project files.

I am using an Altera USB Blaster pod for programming.

I was able to download the .POF file from an old working board from its EPC device. I can program that file into a new board and it works so I know the hardware is good. That file is the same size as a new .POF file I build but they have different data.

I found that the unused pins now default to GND outputs (reading other forum entries) and I fixed that. Are there other things that which changed in the compiler configuration which would affect my design? Any ideas? I am new to FPGA design and there is a lot to absorb. Thanks.

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    I came across a similiar problem recently. We were using Quartus II v4.2 and the project compiled and worked no problem on an Altera EP1K50QC208-3 device. If we compile exactly the same source code using Quartus II v.9.0, the project will compile ok. Download to the same device and the device won't startup and running until few mins later. After that, everything seems to be ok...Since this device is an old device, we don't have the fancy feature like Signal Tap II to look at why it doesn't start up immediately...Any one has any suggestion?