Power Estimation Confidence

Question

Hi,

Can anyone please tell me how to increase Power Estimation Confidence level to high, the below statement is what i get in my compilation report always

Power Estimation Confidence Low: user provided insufficient toggle rate data

can anyone tell me how do i provide sufficient toggle rate data.

altera_forum · Answer

Hi Tausen,

Thanks for the reply, i tried following your method but couldn't figure out few things like

How do you set pin placements in the pin planner
How do you create a clock constraint in the TimeQuest Timing Analyzer

My code is in verilog so do i still need to do the EDA netlist writer settings.

These are some of the warning which i get when i run powerplay analyzer tool

Warning: Node: CLOCK_50 was determined to be a clock but was found without an associated clock assignment.
Warning: Node: state
Warning: Relative toggle rates could not be calculated because no clock domain could be identified for some nodes

Thank You

--- Quote Start ---

Hi kp42,

I have only little knowledge of how Quartus and PowerPlay works, but I've been playing a bit around and I think I'm getting somewhere - here is what I did.

Create project and top-level entity (.vhd file)
Create a testbench - it is important that the stimulus you create in the testbench represents a realistic, typical scenario!
Go to assignments -> settings -> simulation and add a test bench, choose the file you made in the previous step and choose a design instance name you can remember such as "dut" (should match the entity name in the testbench!)
Run compilation and RTL simulation to verify that the design and testbench works
To make PowerPlay happy and remove some warnings, I set up pin placements and clock constraints as well:
Assignments -> pin planner, set pin placements
Open TimeQuest Timing Analyzer and create a clock constraint matching the clock you'll use, make sure you export an sdc file
Under project -> add/remove files in project, add the newly created sdc file to the project
I then set up PowerPlay to write signal activities used, write signal activities to report file, write power dissipation by block to report file. Not yet using an input file.
Running PowerPlay now results in confidence "Low: user provided insufficient toggle rate data"
Back to assignments -> settings, simulation and do some configuration:
Generate VCD file script, under script settings tick "all signals"
Design instance name: set to match entity in testbench, in my case "dut"
Under more EDA netlist writer settings, set architecture name to match architecture in you design (in my case "rtl") and make sure "do not write top level vhdl entity" is off
Finally, run a gate level simulation. This should generate a vcd file in the simulation/modelsim/ directory
Now, back in assignments -> settings -> powerplay, tick "use input file(s)" and add the newly created vcd file
Running PowerPlay now should give you a higher confidence - I'm getting "High: user provided sufficient toggle rate data" with my design now, although it might depend on a number of things that I have no idea about

I've attached my .vhd files so you can see what I mean. The .qsf.txt file contains all my project settings. I'd be happy to share the entire Quartus project as well, but I'm using Quartus II 13.0.1 subscription edition, so I'm not sure if you can actually use it for anything. Let me know if you can.

Good luck!

--- Quote End ---

altera_forum · Answer

--- Quote Start ---

How do you set pin placements in the pin planner

--- Quote End ---

Under assignments, choose pin planner. Then choose a location for each port in the table in the bottom, see screenshot:

https://www.alteraforum.com/forum/attachment.php?attachmentid=9443

If you can't figure this one out, just try without it - I'm not sure its even necessary.

--- Quote Start ---

How do you create a clock constraint in the TimeQuest Timing Analyzer

--- Quote End ---

Open the TimeQuest Timing Analyzer. Click "Create timing netlist". Then go to constraints and click "Create clock" and fill out the details - in my case, name is "clk", period is 10ns, rising edge at 0ns and falling edge at 5ns. Don't forget to export the sdc file.

--- Quote Start ---

My code is in verilog so do i still need to do the EDA netlist writer settings.

--- Quote End ---

Yes - for the "do not write top level vhdl entity"-option, I'm guessing there's something like "do not write top level verilog entity"? I think it is off by default, though, so you might not have to worry about that one option.

--- Quote Start ---

Warning: Node: CLOCK_50 was determined to be a clock but was found without an associated clock assignment.
Warning: Node: state
Warning: Relative toggle rates could not be calculated because no clock domain could be identified for some nodes

--- Quote End ---

Try again once you've created a timing constraint and added the sdc file to the project - that should help.

altera_forum · Answer

Hi Tausen,

I did create a clock constraint of 20ns as in my project and the sdc file was already added before and tried it, but didn't have any changes, it still shows the same result.

Do we need to create a SDC file always whenever we create a clock constraint, if so how do i create it.

Thanks

--- Quote Start ---

Under assignments, choose pin planner. Then choose a location for each port in the table in the bottom, see screenshot:

http://www.alteraforum.com/forum/attachment.php?attachmentid=9443&stc=1

If you can't figure this one out, just try without it - I'm not sure its even necessary.

Open the TimeQuest Timing Analyzer. Click "Create timing netlist". Then go to constraints and click "Create clock" and fill out the details - in my case, name is "clk", period is 10ns, rising edge at 0ns and falling edge at 5ns. Don't forget to export the sdc file.

Yes - for the "do not write top level vhdl entity"-option, I'm guessing there's something like "do not write top level verilog entity"? I think it is off by default, though, so you might not have to worry about that one option.

Try again once you've created a timing constraint and added the sdc file to the project - that should help.

--- Quote End ---

altera_forum · Answer

Hi Tausen,

I created a clock constraint of 20ns as in my project and the SDC file was already added from the earlier attemp, but still the result is the same. Do i need to create a new SDC file whenever i create a clock constraint, if so how do i do it?

altera_forum · Answer

Hi Tausen,

After i added the SDC file as you mentioned, i compiled my project but there two errors being generated which are

Error: Text Design File must contain a Subdesign and Logic Section

Error: Node instance "auto_generated" instantiates undefined entity "mult_rat"

These errors even stop from running PowerPlay Analyzer tool...any suggestions

Thanks

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