Power Estimation Confidence

Hi Tausen,

Thanks for the reply, i tried following your method but couldn't figure out few things like

1. How do you set pin placements in the pin planner

2. How do you create a clock constraint in the TimeQuest Timing Analyzer

My code is in verilog so do i still need to do the EDA netlist writer settings.

These are some of the warning which i get when i run powerplay analyzer tool

• Warning: Node: CLOCK_50 was determined to be a clock but was found without an associated clock assignment.

• Warning: Node: state
• Warning: Relative toggle rates could not be calculated because no clock domain could be identified for some nodes

Thank You

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Hi kp42,

I have only little knowledge of how Quartus and PowerPlay works, but I've been playing a bit around and I think I'm getting somewhere - here is what I did.

• Create project and top-level entity (.vhd file)

• Create a testbench - it is important that the stimulus you create in the testbench represents a realistic, typical scenario!

• Go to assignments -> settings -> simulation and add a test bench, choose the file you made in the previous step and choose a design instance name you can remember such as "dut" (should match the entity name in the testbench!)

• Run compilation and RTL simulation to verify that the design and testbench works

• To make PowerPlay happy and remove some warnings, I set up pin placements and clock constraints as well:

• Assignments -> pin planner, set pin placements

• Open TimeQuest Timing Analyzer and create a clock constraint matching the clock you'll use, make sure you export an sdc file

• Under project -> add/remove files in project, add the newly created sdc file to the project

• I then set up PowerPlay to write signal activities used, write signal activities to report file, write power dissipation by block to report file. Not yet using an input file.

• Running PowerPlay now results in confidence "Low: user provided insufficient toggle rate data"

• Back to assignments -> settings, simulation and do some configuration:

• Generate VCD file script, under script settings tick "all signals"

• Design instance name: set to match entity in testbench, in my case "dut"

• Under more EDA netlist writer settings, set architecture name to match architecture in you design (in my case "rtl") and make sure "do not write top level vhdl entity" is off

• Finally, run a gate level simulation. This should generate a vcd file in the simulation/modelsim/ directory

• Now, back in assignments -> settings -> powerplay, tick "use input file(s)" and add the newly created vcd file

• Running PowerPlay now should give you a higher confidence - I'm getting "High: user provided sufficient toggle rate data" with my design now, although it might depend on a number of things that I have no idea about

I've attached my .vhd files so you can see what I mean. The .qsf.txt file contains all my project settings. I'd be happy to share the entire Quartus project as well, but I'm using Quartus II 13.0.1 subscription edition, so I'm not sure if you can actually use it for anything. Let me know if you can.

Good luck!

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