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WNC_HowardHuang's avatar
WNC_HowardHuang
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3 years ago

possiblity of unstable reset lead to misoperation

Hi, There's a problem that makes us confus. The input reset signal is like this The unstable part would stay about 40 ms long. Here's our source code for trigger Here's the wa...
sstrell's avatar
sstrell
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3 years ago

It certainly could be because of the unstable pulse. Signal Tap can't help with capturing an issue like that. Check your timing analysis. What does your .sdc look like?

But stranger is that there is no way in your design for sig_A to ever go high. Typo in your reset process?

WNC_HowardHuang's avatar
WNC_HowardHuang
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3 years ago

Hi,

Thanks for your replay.

In our design, there's only have clock in .sdc file

create_clock -name CLK25M -period 40.000 -waveform { 0.000 20.000 } [get_ports {FPGA_25M}]
I think there's no error with reset process because reset signal is from outside FPGA.
We'll looking forward to this problem.
Thanks.