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WNC_HowardHuang's avatar
WNC_HowardHuang
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3 years ago

possiblity of unstable reset lead to misoperation

Hi,

There's a problem that makes us confus.

The input reset signal is like this

The unstable part would stay about 40 ms long.

Here's our source code for trigger

Here's the waveform in SignalTap

When sig_A & sig_B is all 0

edge_sig should be 0

But sig_intr appear a pulse when doing reset

Will this situation because of the unstable of reset?

BTW, we also disscuss about the possiblitiy of synchonus reset woule influence sig_intr problem,

but we are not sure if this would be the problem after synthesis or not.

Thanks.

6 Replies

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    3 years ago

    It certainly could be because of the unstable pulse. Signal Tap can't help with capturing an issue like that. Check your timing analysis. What does your .sdc look like?

    But stranger is that there is no way in your design for sig_A to ever go high. Typo in your reset process?

    • WNC_HowardHuang's avatar
      WNC_HowardHuang
      Icon for New Contributor rankNew Contributor
      3 years ago

      Hi,

      Thanks for your replay.

      In our design, there's only have clock in .sdc file

      create_clock -name CLK25M -period 40.000 -waveform { 0.000 20.000 } [get_ports {FPGA_25M}]
      I think there's no error with reset process because reset signal is from outside FPGA.
      We'll looking forward to this problem.
      Thanks.
  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    3 years ago
    In addition, what's the reset source? In case it's asynchronous to clock, you urgently need a reset synchronizer to achieve predictable behaviour.

    Regards
    Frank
    • WNC_HowardHuang's avatar
      WNC_HowardHuang
      Icon for New Contributor rankNew Contributor
      3 years ago

      Hi,

      Thanks for your replay.

      The source of reset is from the other CHIP outside FPGA.

      We guess the unstable waveform might be caused by PCB layout.

      We tried to synchronus reset using shift register

      Then replace original procedure reset part by higher bit of shift register

      So far, the test result seem fine.

      But we think the best way to solve this problem is to figure out the unstable problem of reset.

      Thanks.

  • SyafieqS's avatar
    SyafieqS
    Icon for Super Contributor rankSuper Contributor
    3 years ago

    Higher bit shift register might be a good temporary workaround. But you still need to root cause from outside for unstable pulse. Afraid might cause another issue.


  • SyafieqS's avatar
    SyafieqS
    Icon for Super Contributor rankSuper Contributor
    3 years ago

    I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


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