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WNC_HowardHuang's avatar
WNC_HowardHuang
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3 years ago

possiblity of unstable reset lead to misoperation

Hi, There's a problem that makes us confus. The input reset signal is like this The unstable part would stay about 40 ms long. Here's our source code for trigger Here's the wa...
FvM's avatar
FvM
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3 years ago
In addition, what's the reset source? In case it's asynchronous to clock, you urgently need a reset synchronizer to achieve predictable behaviour.

Regards
Frank
WNC_HowardHuang's avatar
WNC_HowardHuang
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3 years ago

Hi,

Thanks for your replay.

The source of reset is from the other CHIP outside FPGA.

We guess the unstable waveform might be caused by PCB layout.

We tried to synchronus reset using shift register

Then replace original procedure reset part by higher bit of shift register

So far, the test result seem fine.

But we think the best way to solve this problem is to figure out the unstable problem of reset.

Thanks.