Hello, I'm totally new to VHDL and i'm trying to do a polynonamial evaluation. In particular I have a signed 16 bit value (x) and I want to obtain y=d*x^3+c*x^2+b*x+a. I have created a signed multiplier: LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; ENTITY my_signed_multiplier IS PORT( in1, in2 : IN signed (15 DOWNTO 0); clk,clr : IN std_logic; result : OUT signed(15 DOWNTO 0)); END ENTITY my_signed_multiplier; ARCHITECTURE logic OF my_signed_multiplier IS SIGNAL in1_reg, in2_reg : signed (15 DOWNTO 0); SIGNAL out_reg : signed (31 DOWNTO 0); BEGIN PROCESS(clk,clr) BEGIN IF clr ='1' THEN in1_reg<=(OTHERS => '0'); in2_reg<=(OTHERS => '0'); out_reg<=(OTHERS => '0'); ELSIF rising_edge(clk) THEN in1_reg<=in1; in2_reg<=in2; out_reg<=in1_reg*in2_reg; END IF; END PROCESS; result<=out_reg(31 DOWNTO 16); END ARCHITECTURE logic; Now I was supposed to create another entity which has a generic variable (eg: pow : integer ) that specifies how many instance of my_signed multiplier use to obtain the correct signal power elevation. By the way now I'm stuck is I don't know exactly how to do it. Any suggestions is appreciated . Thank you !

Take a step back. Before you start, think about how the circuit would look when created. Then go back and write the code. The multiplier entity you have created will causes a massive bias by just removing the 16 LSBs. Did you intend to do this? and did you intend to floor your results (rather than round to nearest?)

--- Quote Start --- Take a step back. Before you start, think about how the circuit would look when created. Then go back and write the code. The multiplier entity you have created will causes a massive bias by just removing the 16 LSBs. Did you intend to do this? and did you intend to floor your results (rather than round to nearest?) --- Quote End --- Dear Tricky, I have a 16 bit DAC so I'm forced to remove the 16 LSBs. Now I have created 7 multiplier with seven DFF with a generic delay. So that with the multipliers I can evaluate x^7, x^6, x^5...x^0 and, before the final sum (forgetting for now about the coefficients), I compensate the delays introduced by the multipliers with the DFFs. In particular I think that x should be delayed 6 cycles in respect to x^7=((((x*x)*x)*x)*x)*x)*x, x^2 5 cycles and so on. I have noticed that if I sum 8 signal of 16 bit at a time, I need a 24 bit output signal. By the way in VHDL seems that also the summing signals must be 24 bit. Now that I have 8 - 16 bit signals, there is a simple way on promoting them to 24 bit or I must create 8 new 24 bit signal and assignin them the 16 bit ones ? Thank you for your time.

actually, summing 8 16 bit signals, you should only need a 19 bit result. How are you doing the summing? signed/unsigned type do not do any bit extension for you, you have to handle it yourself. It is difficult to understand what you mean without seeing any code. But I worry that with your current method of removing of just removing the 16 LSBs, you wont be summing the results correctly. x^3 is going to be 48 bits wide, with x^2 32 bits. It would be wrong just to sum the 16 MSBs.

Dear Tricky, Yes, you are right, I need a 19 bit result. My fault. This is the code I'm implementing: LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; ENTITY my_poly_test IS PORT( in1 : IN SIGNED (15 DOWNTO 0); clk,clr : IN std_logic; result : OUT SIGNED (15 DOWNTO 0)); END ENTITY my_poly_test; ARCHITECTURE logic OF my_poly_test IS SIGNAL x2 : SIGNED (15 DOWNTO 0); SIGNAL x3 : SIGNED (15 DOWNTO 0); SIGNAL x4 : SIGNED (15 DOWNTO 0); SIGNAL x5 : SIGNED (15 DOWNTO 0); SIGNAL x6 : SIGNED (15 DOWNTO 0); SIGNAL x7 : SIGNED (15 DOWNTO 0); SIGNAL x_d : STD_LOGIC_VECTOR(15 DOWNTO 0); SIGNAL x2_d : STD_LOGIC_VECTOR(15 DOWNTO 0); SIGNAL x3_d : STD_LOGIC_VECTOR (15 DOWNTO 0); SIGNAL x4_d : STD_LOGIC_VECTOR (15 DOWNTO 0); SIGNAL x5_d : STD_LOGIC_VECTOR (15 DOWNTO 0); SIGNAL x6_d : STD_LOGIC_VECTOR (15 DOWNTO 0); SIGNAL x7_d : STD_LOGIC_VECTOR(15 DOWNTO 0); SIGNAL sum : STD_LOGIC_VECTOR(18 DOWNTO 0); COMPONENT my_signed_multiplier IS PORT( in1, in2 : IN signed (15 DOWNTO 0); clk,clr : IN std_logic; result : OUT signed(15 DOWNTO 0)); END COMPONENT; COMPONENT my_generic_dff_aclr IS GENERIC (delay : INTEGER :=4); PORT( d : IN STD_LOGIC_VECTOR(15 DOWNTO 0); clk , clr : IN STD_LOGIC; q: OUT STD_LOGIC_VECTOR(15 DOWNTO 0)); END COMPONENT; COMPONENT my_signed_adder IS PORT( in1,in2 : IN SIGNED (15 DOWNTO 0); clk,clr : IN std_logic; result : OUT SIGNED (15 DOWNTO 0)); END COMPONENT; BEGIN M1 : my_signed_multiplier PORT MAP (in1,in1,clk,clr,x2); M2 : my_signed_multiplier PORT MAP (in1,x2,clk,clr,x3); M3 : my_signed_multiplier PORT MAP (in1,x3,clk,clr,x4); M4 : my_signed_multiplier PORT MAP (in1,x4,clk,clr,x5); M5 : my_signed_multiplier PORT MAP (in1,x5,clk,clr,x6); M6 : my_signed_multiplier PORT MAP (in1,x6,clk,clr,x7); DFF1: my_generic_dff_aclr GENERIC MAP(1) PORT MAP (std_logic_vector(x6),clk,clr,x6_d); DFF2: my_generic_dff_aclr GENERIC MAP(2) PORT MAP (std_logic_vector(x5),clk,clr,x5_d); DFF3: my_generic_dff_aclr GENERIC MAP(3) PORT MAP (std_logic_vector(x4),clk,clr,x4_d); DFF4: my_generic_dff_aclr GENERIC MAP(4) PORT MAP (std_logic_vector(x3),clk,clr,x3_d); DFF5: my_generic_dff_aclr GENERIC MAP(5) PORT MAP (std_logic_vector(x2),clk,clr,x2_d); DFF6: my_generic_dff_aclr GENERIC MAP(6) PORT MAP (std_logic_vector(x),clk,clr,x_d); PROCESS(clk,clr) BEGIN IF clr ='1' THEN x2<=(OTHERS => '0'); x3<=(OTHERS => '0'); x4<=(OTHERS => '0'); x5<=(OTHERS => '0'); x6<=(OTHERS => '0'); x7<=(OTHERS => '0'); x2_d<=(OTHERS => '0'); x3_d<=(OTHERS => '0'); x4_d<=(OTHERS => '0'); x5_d<=(OTHERS => '0'); x6_d<=(OTHERS => '0'); x7_d<=(OTHERS => '0'); ELSIF rising_edge(clk) THEN sum<=1+signed(x2_d)+signed(x3_d)+signed(x4_d)+signed(x5_d)+signed(x6_d)+signed(x7_d); result<=sum(19 DOWNTO 3); END IF; END PROCESS; END ARCHITECTURE logic; Every time I take a mutiplication I take only the 16 MSbs. So at the final sum each signal is exactly 16 bits wide. Thank you for help.

Right, there are going to be many problems here: 1. your "My_signed_multiplier" delay is 2 clocks. So using in1 directly to each multiplier stage is going to mean x3 is going to be x2 multiplied by the value of in1 2 clocks after the value of in1 to create x2. So you need to create pipelined versions of the input to allign it properly. 2. You cannot clear x2-7 and xN_d in the other process - they are assigned from the components. This will cause multiple driver errors 3. You've got the magnitude problem I mentioned in my previous post when doing the sum. What you're doing is like this: lets imagin we have X^3 + X^2 + X + 7, and say X is 25. THe answer should be 16282. SO, according to your code: X^3 = 15625, lets lose the 2 LSBs (as we're doing 2 mults), we get 156. X^2 = 625, lets lose the LSB, we get 62 so 156 + 62 + 25 + 7 = 250. Nothing like the actual answer, even if we dropped the 2 LSBs from the correct answer. You need to pay attention to bit allignment when you do the multiplies and adds. Otherwise you end up adding values together that are orders of magnitude apart. 4. Other coding stype point: Please use named association in entity instantiation rather than positional (plus if you want to, ditch the component declarations all together and go with direct instantiation): eg: my_ent_inst : entity work.my_ent generic map ( some_generic => 1, --etc ) port map ( portA => input1, portB => input2, --etc ) It is less prone to the annoying errors you get with positional. (And for direct instantiation, the compiler checks the entity matches the instantiation, rather than the component declaration, so you get an instant error if there is a missmatch, rather than waiting for the error to pop out during elaboration which can be several minutes later).

Polynomial Evaluation | Altera Community

25 Replies

Altera_Forum

Honored Contributor

12 years ago

--- Quote Start ---

Hello guys,

I've modified my vhdl code as you suggested. Hope it works and that all is finally ok !

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY my_poly_test IS
    PORT( in1 : IN SIGNED (15 DOWNTO 0);
                clk,clr : IN std_logic;
             result : OUT SIGNED (15 DOWNTO 0));
END ENTITY my_poly_test;
ARCHITECTURE logic OF my_poly_test IS
    SIGNAL x2 : SIGNED (15 DOWNTO 0);
    SIGNAL x3 : SIGNED (15 DOWNTO 0);
    SIGNAL x4 : SIGNED (15 DOWNTO 0);
    SIGNAL x5 : SIGNED (15 DOWNTO 0);
    SIGNAL x6 : SIGNED (15 DOWNTO 0);
    SIGNAL x7 : SIGNED (15 DOWNTO 0);
    SIGNAL in1_1d : STD_LOGIC_VECTOR(15 DOWNTO 0);
    SIGNAL in1_2d : STD_LOGIC_VECTOR(15 DOWNTO 0);
    SIGNAL in1_3d  : STD_LOGIC_VECTOR (15 DOWNTO 0);
    SIGNAL in1_4d : STD_LOGIC_VECTOR (15 DOWNTO 0);
    SIGNAL in1_5d : STD_LOGIC_VECTOR (15 DOWNTO 0);
    SIGNAL x_6d : STD_LOGIC_VECTOR(15 DOWNTO 0);
    SIGNAL x2_5d : STD_LOGIC_VECTOR(15 DOWNTO 0);
    SIGNAL x3_4d : STD_LOGIC_VECTOR (15 DOWNTO 0);
    SIGNAL x4_3d : STD_LOGIC_VECTOR (15 DOWNTO 0);
    SIGNAL x5_2d : STD_LOGIC_VECTOR (15 DOWNTO 0);
    SIGNAL x6_1d : STD_LOGIC_VECTOR (15 DOWNTO 0);
    SIGNAL x7_d : STD_LOGIC_VECTOR(15 DOWNTO 0);
    SIGNAL sum : SIGNED(31 DOWNTO 0);
    
              
    BEGIN
        M1 :   work.my_signed_multiplier PORT MAP (in1=>in1,in2=>in1,clk=>clk,clr=>clr,result=>x2);
        
        DFF1:  work.my_generic_dff_aclr GENERIC MAP(delay =>1) PORT MAP (d => std_logic_vector(in1), clk => clk, clr=> clr, q => in1_1d);
       M2 :   work.my_signed_multiplier PORT MAP (in1=> signed(in1_1d),in2=> x2,clk=>clk,clr=>clr,result => x3);
        
        DFF2:  work.my_generic_dff_aclr GENERIC MAP(delay =>1) PORT MAP (d => in1_1d,clk => clk,clr=> clr,q =>in1_2d);
        M3 :   work.my_signed_multiplier PORT MAP (in1=> signed(in1_2d),in2=>x3,clk=>clk,clr=>clr,result => x4);
        
        DFF3:  work.my_generic_dff_aclr GENERIC MAP(delay =>1) PORT MAP (d =>in1_2d,clk => clk,clr=> clr,q =>in1_3d);
        M4 :   work.my_signed_multiplier PORT MAP (in1=> signed(in1_3d),in2=>x4,clk=>clk,clr=>clr,result => x5);
        
        DFF4:  work.my_generic_dff_aclr GENERIC MAP(delay =>1) PORT MAP (d => in1_3d,clk =>clk,clr=> clr,q =>in1_4d);
        M5 :   work.my_signed_multiplier PORT MAP (in1=> signed(in1_4d),in2=>x5,clk=>clk,clr=>clr,result => x6);
        
        DFF5:  work.my_generic_dff_aclr GENERIC MAP(delay =>1) PORT MAP (d => in1_4d,clk =>clk,clr=> clr,q =>in1_5d);
        M6 :   work.my_signed_multiplier PORT MAP (in1=> signed(in1_5d),in2=>x6,clk=>clk,clr=>clr,result => x7);
        
        DFF6:  work.my_generic_dff_aclr  GENERIC MAP(delay =>1) PORT MAP (d => std_logic_vector(x6), clk => clk, clr=> clr, q =>x6_1d);
        DFF7:  work.my_generic_dff_aclr  GENERIC MAP(delay =>2) PORT MAP (d => std_logic_vector(x5), clk => clk, clr=> clr, q =>x5_2d);
        DFF8:  work.my_generic_dff_aclr  GENERIC MAP(delay =>3) PORT MAP (d => std_logic_vector(x4), clk => clk, clr=> clr, q =>x4_3d);
        DFF9:  work.my_generic_dff_aclr  GENERIC MAP(delay =>4) PORT MAP (d => std_logic_vector(x3), clk => clk, clr=> clr, q =>x3_4d);
        DFF10: work.my_generic_dff_aclr GENERIC MAP(delay =>5) PORT MAP (d => std_logic_vector(x2), clk => clk, clr=> clr, q =>x2_5d);
        DFF11: work.my_generic_dff_aclr GENERIC MAP(delay =>6) PORT MAP (d => std_logic_vector(in1), clk => clk, clr=> clr,q =>x_6d);
    PROCESS(clk,clr)
    BEGIN
        IF clr ='1' THEN
        result<=(OTHERS => '0');
        
        ELSIF rising_edge(clk) THEN
            sum<=1+signed(("0000000000000000")&x_6d)+signed(x2_5d&("0000000000000000"))+signed(x3_4d&("0000000000000000"))+signed(x4_3d&("0000000000000000"))+signed(x5_2d&("0000000000000000"))+signed(x6_1d&("0000000000000000"))+signed(x7_d&("0000000000000000"));
            result<=sum(31 DOWNTO 16);
        END IF;    
    END PROCESS;
END ARCHITECTURE logic;

Thank you for your help !

--- Quote End ---

There are some misunderstandings from you.

1)You only need add leading zeros to sum final result and not inputs to adder as you did.

2)why divide back the result. you add zeros then remove them? what is the point

for accurate result you need all bits. if you want 16 bits final output then it implies you want scaled version in which case you don't need to add zeros then remove them

3) adding 1 is wrong. it should become zero and should not affect the result as it has lost that sort of accuracy

Altera_Forum
Honored Contributor
12 years ago
--- Quote Start ---
Instead of asking us if it works - how about testing it yourself and learning the tools?
--- Quote End ---

I'm doing it Tricky. I'm using Quartus II with the university Program VWF. But I'm totally new also to it. I started with vhdl and testbench two days ago.. Also a little hint could give me the right direction.

@Kaz, I need only 16 bit at the final sum as I have a 16 bit dac so at the output of the polynomial I MUST have a 16 bit signal.
So as I have understood from your last post I do not need the leading zeros in the signals input of the sum and also at the output signal.. Am I right ?

Thank you for your time !
Altera_Forum
Honored Contributor
12 years ago
--- Quote Start ---

@Kaz, I need only 16 bit at the final sum as I have a 16 bit dac so at the output of the polynomial I MUST have a 16 bit signal.
So as I have understood from your last post I do not need the leading zeros in the signals input of the sum and also at the output signal.. Am I right ?

Thank you for your time !
--- Quote End ---

you are right.
with only 16 bit resolution you are dealing with scaled down result(not absolute values).
A constant term must also be scaled down by 2^16 before entering addition and so you can just ignore it.
Altera_Forum
Honored Contributor
12 years ago
--- Quote Start ---
I'm doing it Tricky. I'm using Quartus II with the university Program VWF. But I'm totally new also to it. I started with vhdl and testbench two days ago.. Also a little hint could give me the right direction.

--- Quote End ---

Stop using the VWF file and write your own VHDL testbench. There are many examples on the web. With a testbench you can write code that is completly unsynthesisable as long as it gets the job done. An example for generating a clock:

signal clk : std_logic := '0';

clk <= not clk after 5 ns; -- a 100 MHz clock.

This way you can control the input data using text files (using the textio library - give it a google - lots of tutorials), and monitor or even log the output to a log file.
Altera_Forum
Honored Contributor
12 years ago
--- Quote Start ---
Stop using the VWF file and write your own VHDL testbench. There are many examples on the web. With a testbench you can write code that is completly unsynthesisable as long as it gets the job done. An example for generating a clock:

signal clk : std_logic := '0';

clk <= not clk after 5 ns; -- a 100 MHz clock.

This way you can control the input data using text files (using the textio library - give it a google - lots of tutorials), and monitor or even log the output to a log file.
--- Quote End ---

Thank you tricky. I will check also for this.

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