--- Quote Start ---
Stop using the VWF file and write your own VHDL testbench. There are many examples on the web. With a testbench you can write code that is completly unsynthesisable as long as it gets the job done. An example for generating a clock:
signal clk : std_logic := '0';
clk <= not clk after 5 ns; -- a 100 MHz clock.
This way you can control the input data using text files (using the textio library - give it a google - lots of tutorials), and monitor or even log the output to a log file.
--- Quote End ---
Thank you tricky. I will check also for this.
Honored Contributor
