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Hello guys,
I've modified my vhdl code as you suggested. Hope it works and that all is finally ok !
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY my_poly_test IS
PORT( in1 : IN SIGNED (15 DOWNTO 0);
clk,clr : IN std_logic;
result : OUT SIGNED (15 DOWNTO 0));
END ENTITY my_poly_test;
ARCHITECTURE logic OF my_poly_test IS
SIGNAL x2 : SIGNED (15 DOWNTO 0);
SIGNAL x3 : SIGNED (15 DOWNTO 0);
SIGNAL x4 : SIGNED (15 DOWNTO 0);
SIGNAL x5 : SIGNED (15 DOWNTO 0);
SIGNAL x6 : SIGNED (15 DOWNTO 0);
SIGNAL x7 : SIGNED (15 DOWNTO 0);
SIGNAL in1_1d : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL in1_2d : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL in1_3d : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL in1_4d : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL in1_5d : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL x_6d : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL x2_5d : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL x3_4d : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL x4_3d : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL x5_2d : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL x6_1d : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL x7_d : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL sum : SIGNED(31 DOWNTO 0);
BEGIN
M1 : work.my_signed_multiplier PORT MAP (in1=>in1,in2=>in1,clk=>clk,clr=>clr,result=>x2);
DFF1: work.my_generic_dff_aclr GENERIC MAP(delay =>1) PORT MAP (d => std_logic_vector(in1), clk => clk, clr=> clr, q => in1_1d);
M2 : work.my_signed_multiplier PORT MAP (in1=> signed(in1_1d),in2=> x2,clk=>clk,clr=>clr,result => x3);
DFF2: work.my_generic_dff_aclr GENERIC MAP(delay =>1) PORT MAP (d => in1_1d,clk => clk,clr=> clr,q =>in1_2d);
M3 : work.my_signed_multiplier PORT MAP (in1=> signed(in1_2d),in2=>x3,clk=>clk,clr=>clr,result => x4);
DFF3: work.my_generic_dff_aclr GENERIC MAP(delay =>1) PORT MAP (d =>in1_2d,clk => clk,clr=> clr,q =>in1_3d);
M4 : work.my_signed_multiplier PORT MAP (in1=> signed(in1_3d),in2=>x4,clk=>clk,clr=>clr,result => x5);
DFF4: work.my_generic_dff_aclr GENERIC MAP(delay =>1) PORT MAP (d => in1_3d,clk =>clk,clr=> clr,q =>in1_4d);
M5 : work.my_signed_multiplier PORT MAP (in1=> signed(in1_4d),in2=>x5,clk=>clk,clr=>clr,result => x6);
DFF5: work.my_generic_dff_aclr GENERIC MAP(delay =>1) PORT MAP (d => in1_4d,clk =>clk,clr=> clr,q =>in1_5d);
M6 : work.my_signed_multiplier PORT MAP (in1=> signed(in1_5d),in2=>x6,clk=>clk,clr=>clr,result => x7);
DFF6: work.my_generic_dff_aclr GENERIC MAP(delay =>1) PORT MAP (d => std_logic_vector(x6), clk => clk, clr=> clr, q =>x6_1d);
DFF7: work.my_generic_dff_aclr GENERIC MAP(delay =>2) PORT MAP (d => std_logic_vector(x5), clk => clk, clr=> clr, q =>x5_2d);
DFF8: work.my_generic_dff_aclr GENERIC MAP(delay =>3) PORT MAP (d => std_logic_vector(x4), clk => clk, clr=> clr, q =>x4_3d);
DFF9: work.my_generic_dff_aclr GENERIC MAP(delay =>4) PORT MAP (d => std_logic_vector(x3), clk => clk, clr=> clr, q =>x3_4d);
DFF10: work.my_generic_dff_aclr GENERIC MAP(delay =>5) PORT MAP (d => std_logic_vector(x2), clk => clk, clr=> clr, q =>x2_5d);
DFF11: work.my_generic_dff_aclr GENERIC MAP(delay =>6) PORT MAP (d => std_logic_vector(in1), clk => clk, clr=> clr,q =>x_6d);
PROCESS(clk,clr)
BEGIN
IF clr ='1' THEN
result<=(OTHERS => '0');
ELSIF rising_edge(clk) THEN
sum<=1+signed(("0000000000000000")&x_6d)+signed(x2_5d&("0000000000000000"))+signed(x3_4d&("0000000000000000"))+signed(x4_3d&("0000000000000000"))+signed(x5_2d&("0000000000000000"))+signed(x6_1d&("0000000000000000"))+signed(x7_d&("0000000000000000"));
result<=sum(31 DOWNTO 16);
END IF;
END PROCESS;
END ARCHITECTURE logic;
Thank you for your help !
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There are some misunderstandings from you.
1)You only need add leading zeros to sum final result and not inputs to adder as you did.
2)why divide back the result. you add zeros then remove them? what is the point
for accurate result you need all bits. if you want 16 bits final output then it implies you want scaled version in which case you don't need to add zeros then remove them
3) adding 1 is wrong. it should become zero and should not affect the result as it has lost that sort of accuracy
Honored Contributor
