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sgulh's avatar
sgulh
Icon for New Contributor rankNew Contributor
7 years ago

pls provide me verilog code for led rotate on fpga

i have de 2 115 fpga i need led rotate verilog code

3 Replies

  • AnandRaj_S_Intel's avatar
    AnandRaj_S_Intel
    Icon for Regular Contributor rankRegular Contributor

    Hi,

    You can achieve it with simple ring counter and delay logic.

    For more information refer below logic or you can google it.

    //To create the frequencies needed:
    // Input clock is 25 kHz, chosen arbitrarily.
    // Formula is: (25 kHz / 100 Hz * 50% duty cycle)
    // So for 100 Hz: 25,000 / 100 * 0.5 = 125
    //operate the below logic from requried clock        
     if(clr==1)           
                q<=4′b1000;      
     else            begin                
                q[3]<=q[0];                
                q[2]<=q[3];               
                q[1]<=q[2];                
                q[0]<=q[1];            
     end

    Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

    Best Regards,

    Anand Raj Shankar

    (This message was posted on behalf of Intel Corporation)

  • AnandRaj_S_Intel's avatar
    AnandRaj_S_Intel
    Icon for Regular Contributor rankRegular Contributor

    Hi,

    Above code is not complete, you have to complete.

    1. Have you inserted clock?
    2. At what frequency your design works?
    3. What is not working in above code?

    You need to work with Modelsim first and try to understand coding.​

    // Quartus Prime Verilog Template
    // One-bit wide, N-bit long shift register
     
    module basic_rot_register 
    (
    	input clk, enable,
    	input sr_in,
    	output sr_out
    );
     
    	// Declare the rotate register
    	reg [3:0] sr;
       reg [23:0] count=0;
    	reg clk_out=1'b0;
    	// Shift everything over, load the incoming bit
    	always @ (posedge clk_out)
    	begin
    		if (enable == 1'b1)
    			sr<=4'b1000;
    		else
    		begin
    			sr[3:1] <= sr[2:0];
    			sr[0] <= sr[3];
    		end
    	end
     
    	// Catch the outgoing bit
    	assign sr_out = sr;
    	
    always @(posedge clk) begin
       count <= count + 1;
       if(count == 10000000)//5hz
       begin
          count<=0;
          clk_out <= !clk_out;
       end
    end
     
    endmodule

    Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

    Best Regards,

    Anand Raj Shankar

    (This message was posted on behalf of Intel Corporation)

  • sgulh's avatar
    sgulh
    Icon for New Contributor rankNew Contributor

    thanks for reply but given code not working i tried it on google but