PLL seperate design unit different between Quartus and Modelsim

Hello everyone,

I have yet another problem with Quartus and this time with Modelsim as well.
In my design I use a PLL which I inserted via a Megawizard IP Core.

The problem is, that Quartus adds a separate design unit for the IP core and does not add it in work. This causes problems while trying to run Modelsim. While replacing the file with the simulation file it adds the pll into the work design unit and thus is not able to find it under the unit that Quartus uses.

So whenever I want to switch from Modelsim to Quartus I have to change my file which gets annoying really fast. Is there a workaround to avoid that?

I have attached the changes below for better understanding.

Best regards
Christian

Quartus:

library NNFPGA_PLL;
use NNFPGA_PLL.all;

entity NNFPGA_neuralNetwork is
port (...);

end NNFPGA_neuralNetwork;


architecture behave of NNFPGA_neuralNetwork is
...
signal subClock : std_logic;
signal locked : std_logic;
...

begin
PLL : entity NNFPGA_PLL.NNFPGA_PLL
port map(refclk => clk,
rst => rst,
outclk_0 => subClock,
locked => locked);

...

end behave;

Modelsim:

--library NNFPGA_PLL;
--use NNFPGA_PLL.all;

entity NNFPGA_neuralNetwork is
port (...);

end NNFPGA_neuralNetwork;


architecture behave of NNFPGA_neuralNetwork is
...
signal subClock : std_logic;
signal locked : std_logic;
...

begin
PLL : entity work.NNFPGA_PLL
port map(refclk => clk,
rst => rst,
outclk_0 => subClock,
locked => locked);

...

end behave;