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Altera_Forum
Honored Contributor
Honored ContributorPll reconfiguration
Hi,
I have met two problems when dealing with dynamic reconfiguration of pll for Cyclone IV devices. 1. When I dynamically reconfigured PLL, I found that unwanted signals are generating between rising edge of "scandone" and falling edge of "Locked". What would be the reason for that? (when Locked signal is Low, the output of "c0" is "X"). 2. Even though the "locked" is high, the output of PLL is not phase aligned with the inclk0. After certain time delay it will eventually aligned in phase with inclk0. Why that "c0" is not phase aligned with "inclk0" when locked is high? Thanks in advance Praful Ramesh O3 Replies
Altera_Forum2. I've found that I need to assert an areset after dynamically configuring a pll to get the inputs/outputs properly phase aligned.
- Altera_Forum
Thank you.. it worked.. :)
- Altera_Forum
It would be a good practice to perform a reset after dynamic reconfiguration to ensure correct functionality of the PLL. The same applies to transceiver PLL as well.
