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adamShiau's avatar
adamShiau
Icon for New Contributor rankNew Contributor
2 years ago
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PLL output pins question

Hi everyone, I have a Cyclone IV (EP4CE15F17) FPGA board that uses a 50MHz clock input fed to a PLL. It then generates three clocks for ADC、DAC and SDRAM。 The clock pin assignment is as below , a...
Hdl
  • FvM's avatar
    FvM
    2 years ago

    Hi,
    sure you need dedicated clock outputs for all three clocks?

    If so, separate PLLs are required each output. Input to the PLLs can be provided in different ways. If performance of the clock outputs is as critical as you assume, they should be probably fed by direct clock inputs. Propagating the reference clock through clock network will also involve jitter and delay skew.

    It would be however better to rote a single reference clock input to all PLLs than cascading PLLs.

FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
2 years ago

Hi,
sure you need dedicated clock outputs for all three clocks?

If so, separate PLLs are required each output. Input to the PLLs can be provided in different ways. If performance of the clock outputs is as critical as you assume, they should be probably fed by direct clock inputs. Propagating the reference clock through clock network will also involve jitter and delay skew.

It would be however better to rote a single reference clock input to all PLLs than cascading PLLs.