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adamShiau's avatar
adamShiau
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2 years ago
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PLL output pins question

Hi everyone, I have a Cyclone IV (EP4CE15F17) FPGA board that uses a 50MHz clock input fed to a PLL. It then generates three clocks for ADC、DAC and SDRAM。 The clock pin assignment is as below , a...
Hdl
  • FvM's avatar
    FvM
    2 years ago

    Hi,
    sure you need dedicated clock outputs for all three clocks?

    If so, separate PLLs are required each output. Input to the PLLs can be provided in different ways. If performance of the clock outputs is as critical as you assume, they should be probably fed by direct clock inputs. Propagating the reference clock through clock network will also involve jitter and delay skew.

    It would be however better to rote a single reference clock input to all PLLs than cascading PLLs.

FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
2 years ago

Hi,
the difference is between dedicated clock output and I/O pin fed through global clock network. According to the quoted device handbook information, all three outputs are non-dedicated clock outputs. They involve higher jitter and delay skew than dedicated outputs but most likely will work well for your application.

adamShiau's avatar
adamShiau
Icon for New Contributor rankNew Contributor
2 years ago

Hi FvM,

Thank you for the response.

In my case, if I want to generate three dedicated clock outputs to an external device using only one clock input, do I need to physically connect the input clock pin to three PLL inputs (via PCB trace) and assign the PLL#_CLKOUT of each PLL to PLL output counter C[0]?

Alternatively, can I internally connect PLL output counters other than PLL C[0] to inputs of other PLL instances (via FPGA interconnection fabric) and then derive C[0] as an external clock output?"

Adam.S