PLL is not fully compensated . . .

Hi kaz,

to answer a little bit more detailed:

I have this one clock in pin available and connect it directly to 2 PLLs. In my Design I have several different clock rates. So I decided to use the avilable PLLs in order to make the Timing analysis easier by just using "derive_pll_clocks -create_base_clocks" in my sdc file.

Now, I see that it was not meant to conneckt more than 1 PLL to a dedicated clock input pin, is that right?

So I guess I have to generate just a subset of my needed clock rates and use clock enables to get the rest of my system be clocked as needed. I cannot change the hardware anymore since this development is long finished . . .

Regards,

Maik