Honored ContributorHi,
anybody please help me to write Verilog code to generate varying frequencies using pll and counter based frequency synthesizer. please suggest me appropriate link Thak you
Honored ContributorI'm not sure you state you requirements very clearly. You mention PLLs and counters. Are you expecting to use the PLL to generate a high frequency clock and counters to divide that clock down to the 'synthesised' frequency of choice?
Assuming so - a simple solution: Use Altera's Megawizard to generate a PLL for the particular FPGA family you're targeting. Generate a high frequency clock and feed dividing logic to generate lower frequency clocks. The following link includes simple code to divide down a clock: http://www.asic-world.com/examples/verilog/divide_by_2.html (http://www.asic-world.com/examples/verilog/divide_by_2.html) Regards, Alex
