PLL and dedicated input problem

Hello,

I have a little trouble with clock and PLL. I use a Stratix III FPGA (EP3SE260F) that receive a clock from external. This signal is furnish to a PLL (in Normal mode) that generates a high frequency clock for the system. My problem is that I got this warning :

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Critical Warning: Input pin "[pin_name]" feeds inclk port of PLL "[PLL_inst_name]|altpll:altpll_component|pll" by global clock - I/O timing will be affected

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I saw the solution on altera support (http://www.altera.com/support/kdb/solutions/rd01252008_712.html) (http://www.altera.com/support/kdb/solutions/rd01252008_712.html%29), but everything is not clear.

If I set the PLL is No Compensation Mode, I have no more this warning but still this other one, and I don't understand the info message :

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Warning: PLL "[PLL_inst_name]|altpll:altpll_component|pll" input clock inclk[0] may have reduced jitter performance because it is fed by a non-dedicated input.

Info: Input port INCLK[0] of node PLL "[PLL_inst_name]|altpll:altpll_component|pll" is driven by HSTCA_CLKIN_2~inputclkctrl which is OUTCLK output port of Clock enable block type node HSTCA_CLKIN_2~inputclkctrl

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The external clock arrives on the pin AP18 which correspond to signal CLK4n. According to Table 6-7 of the Stratix III Device Handbook, this clock is dedicated for PLLs B1 and B2.

I check the compilation report in Quartus, and the PLL chosen is well the B1, so the clock should be effectively dedicated for this PLL, but Quartus told also that the signal type of the input is a global clock. Still from Stratix III Handbook, it is stated :

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The input and output delays are fully compensated by a PLL only when they are using the dedicated clock input pins associated with a given PLL as the clock source.

...

When an RCLK or GCLK network drives the PLL, the input and output delays may not be fully compensated in the Quartus II software.

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So it appears that the input signal is in the same time a global clock and a dedicated clock for the PLL. If somebody can enlighten me on this.

Thanks in advance.

Jérôme