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Altera_Forum
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15 years ago

PLL and dedicated input problem

Hello, I have a little trouble with clock and PLL. I use a Stratix III FPGA (EP3SE260F) that receive a clock from external. This signal is furnish to a PLL (in Normal mode) that generates a hig...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I think, the messages are pretty clear. The respective PLL can be driven only by a routed clock (the PLL position is fixed most likely because if it's output connections or specific function, you didn't tell). It can't use one of it's associated clock inputs, so it has reduced timing compensation respectively jitter performance. In most cases it's no issue, simply accept it.