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Altera_Forum
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15 years ago

PLL and dedicated input problem

Hello, I have a little trouble with clock and PLL. I use a Stratix III FPGA (EP3SE260F) that receive a clock from external. This signal is furnish to a PLL (in Normal mode) that generates a hig...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Can CLK4n drive PLL input in Stratix III? Because in Stratix IV it can drive only GCLK but CLK4p can drive PLL input. If this is the case then it's clear why your PLL input is driven by GCLK.