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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

pleez,, URGENT!! about loops in verilog?

Hey all;

I'm trien to write a loop in verilog to initialize all the entries in an array of 128 to a value of zero,

and I'm having the following error:

procedural continuous assignment to register is not supported

====================================

here is my code ::

====================================

// Instruction Memory

module imem(clk, reset, wr_enable,fetch_enable, mem_out, address, mem_in);

input clk;

input reset;

input wr_enable;

input fetch_enable; // this will control startin or stopin running stored commands

input [4:0] address;

output [31:0]mem_out;

input [31:0]mem_in;

reg [31 :0]mem_out;

reg [31 :0]array_reg[127:0]; //can save 128 instruction

integer i;

initial

while(i< 128)

begin

assign i = i+1;

mem_out[i]<= 32'hfffff;

end

always @(posedge clk)

begin

if(fetch_enable)

begin

if (reset)

begin

mem_out <= 32'd0;

end

else

if(!wr_enable)

begin

mem_out <= array_reg[address];

end

else

array_reg[address] <= mem_in;

end

end

endmodule

===================================

thaanks in advance :)

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    Hi,

    I think in general it's not a good idea to try to synthesize loops like the one you have created. If you are wondering why, try to think of how your code could be converted into hardware.

    Also, don't use "initial" blocks when synthesizing, only when testbenching. Whatever you want to be done initially should be triggered by the reset or done when coming out of reset.

    Seeing that you are looking to create 512 bytes of memory, you could just specify a memory block in the mega wizard and instantiate it in your code.

    Just for kicks though, you could create a counter which selects the which register to write the initial value. Then, in an always block triggered by both the posedge of clock and negedge of reset, you could: 1) take the counter out of reset when the reset goes high, 2)on each clock pulse write to the register who's index is the counter value, 3) when the counter has passed the last register, put the counter back into reset and set a done flag so that you can get on with your other logic.

    I would also recommend that you go over some more unrelated example designs in Verilog.

    Let me know if it works.

    Andrew
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    --- Quote Start ---

    Hey all;

    I'm trien to write a loop in verilog to initialize all the entries in an array of 128 to a value of zero,

    and I'm having the following error:

    procedural continuous assignment to register is not supported

    ====================================

    here is my code ::

    ====================================

    // Instruction Memory

    module imem(clk, reset, wr_enable,fetch_enable, mem_out, address, mem_in);

    input clk;

    input reset;

    input wr_enable;

    input fetch_enable; // this will control startin or stopin running stored commands

    input [4:0] address;

    output [31:0]mem_out;

    input [31:0]mem_in;

    reg [31 :0]mem_out;

    reg [31 :0]array_reg[127:0]; //can save 128 instruction

    integer i;

    initial

    while(i< 128)

    begin

    assign i = i+1;

    mem_out<= 32'hfffff;

    end

    always @(posedge clk)

    begin

    if(fetch_enable)

    begin

    if (reset)

    begin

    mem_out <= 32'd0;

    end

    else

    if(!wr_enable)

    begin

    mem_out <= array_reg[address];

    end

    else

    array_reg[address] <= mem_in;

    end

    end

    endmodule

    ===================================

    thaanks in advance :)

    --- quote end ---

    hi,

    you are using the assign statement with an integer. that's not allowed.

    assign i = i+1 --> change to i = i + 1;

    do really want to initialize "mem_out". "mem_out" is already set to a defined state

    with the reset signal.

    in case you would like to init your ram "array_reg" change your code to :

    integer i;

    integer p;

    initial

    begin

    i = i+1;

    p = 128;

    for (i=0; i<p; i=i+1)

    array_reg<= 32'hffffffff;

    end

    Using "while" is not recommended.

    Have a look into the "db" folder. You will find a so-called <>.mif file. Look into the file and you could see the init values for the ram.

    Kind regards

    GPK