pleez,, URGENT!! about loops in verilog?

Hi,

I think in general it's not a good idea to try to synthesize loops like the one you have created. If you are wondering why, try to think of how your code could be converted into hardware.

Also, don't use "initial" blocks when synthesizing, only when testbenching. Whatever you want to be done initially should be triggered by the reset or done when coming out of reset.

Seeing that you are looking to create 512 bytes of memory, you could just specify a memory block in the mega wizard and instantiate it in your code.

Just for kicks though, you could create a counter which selects the which register to write the initial value. Then, in an always block triggered by both the posedge of clock and negedge of reset, you could: 1) take the counter out of reset when the reset goes high, 2)on each clock pulse write to the register who's index is the counter value, 3) when the counter has passed the last register, put the counter back into reset and set a done flag so that you can get on with your other logic.

I would also recommend that you go over some more unrelated example designs in Verilog.

Let me know if it works.

Andrew