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FHint's avatar
FHint
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Platform designer very slow when opening top level system (21.1 Std)

Hello, I am currently working on a FPGA project with the Quartus Prime Standard 21.1 software. When opening the top level QSYS-file it takes forever to finally finish (multiple hours). I have test...
Compilation
Hdl
Platform
RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

Could you help to share your design .qar file (Project> Achieve Project) so we could investigate further?


Best Regards,

Richard Tan


  • FHint's avatar
    FHint
    Icon for Occasional Contributor rankOccasional Contributor
    3 years ago

    Unfortunately, as mentioned in the original post, I am not able to share the design files due to corporate regulations.

    The only way would be by sharing via a secure platform, singing NDA and so on.

    Best regards,
    Florian