Forum Discussion
Matt37
New Contributor
New ContributorPlatform Designer: SV Interfaces and IP Instantiation
I’m working on a user register map with an Avalon interface that will be instantiated as a component inside Platform Designer.
The issue is that when I use a struct for the Avalon interface, the tools only generate plain Verilog code, which doesn’t allow for SystemVerilog structs. Are there any solutions or recommendations?
I already tried to include the package. Also, I couldn't find any information on a specific argument for the tcl instantiation of the component.
Thank you in advance.
2 Replies
FvMSuper Contributor
Hi,
I would be glad if there's an option to export structured interfaces from Platform Designer IP to my HDL code through conduits. But I take it as granted that conduits are restricted to one-dimensional vectors. The solution is to create a mapping between your structure and a large vector.
Regards
Frank
Matt37Thank you for your time, we conclude the same thing. It would be awesome that specific feature.
