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Schroeti's avatar
Schroeti
Icon for Occasional Contributor rankOccasional Contributor
5 years ago
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Platform designer interconnect: unexpected behavior

Hi.

Now i have a strange problem within the memory mapped domain of a platform designer system design. The system comprises 2 masters and 4 slaves.

After one of the master issues it's first write command, the interconnect fabric responds way too much writeresponsevalid counts.

The same applies to the readdatavalid signal.

Furthermore, after the first read goes to the interconnect, the addressed slave gets too much reads.

The interconnect read and write responses are asserted before the slave responds.

I'm using Quartus 20.3 pro.

Why is this and how can i change it to the right behavior?

Thanks
Philipp

  • Schroeti's avatar
    Schroeti
    5 years ago

    Finally i found the bug. It was an error in the _hw.tcl script of the new custom agent: the writeresponsevalid was declared as writeresponsevalid_n.

    @sstrell : Thanks for your effort!

8 Replies

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    5 years ago

    (Host = master, agent = slave)

    I'm not sure if this is part of the problem and it's a little tricky to see, but in the first two waveform pictures (issue 0 and issue 2), it looks like your host is not honoring waitrequest correctly. The write_o enable signal, along with the address and write data, should be held as long as waitrequest is high. Are both the host and agent your own custom components?

    • Schroeti's avatar
      Schroeti
      Icon for Occasional Contributor rankOccasional Contributor
      5 years ago

      In issue1 you can see that the write signal is sampled high one clock period before the waitrequest is sampled high. The avalon-mm specification states that the waitrequest is asserted asynchronously with read or write. That means in case of a waitrequest they should be samled high at the same time, right? This would also correspond to the waitrequest allowance setting of 0.

      Yes, both the host and agent are custom components.

      The host is functioning as follows: There is a look-ahead FIFO issuing data which contains address, byteenable, writedata, read and write signals. Additionally, the read and write signals are ANDed with the valid output of the FIFO. The FIFO is read if the waitrequest is low.
      To my understanding this should be proper. The host runs error-free in another system.

      • sstrell's avatar
        sstrell
        Icon for Super Contributor rankSuper Contributor
        5 years ago

        Very odd. At first I was thinking this was perhaps a pipelining issue, but you're only issuing a single read command from the host. In the issue 0 diagram, is waitrequest from the agent correct? It keeps going high and low while the interconnect continues asserting the read enable signal to it. Each time it releases waitrequest, the interconnect would think that valid read data was available.