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Schroeti's avatar
Schroeti
Icon for Occasional Contributor rankOccasional Contributor
5 years ago
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Platform designer interconnect: unexpected behavior

Hi. Now i have a strange problem within the memory mapped domain of a platform designer system design. The system comprises 2 masters and 4 slaves. After one of the master issues it's first write...
  • Schroeti's avatar
    Schroeti
    5 years ago

    Finally i found the bug. It was an error in the _hw.tcl script of the new custom agent: the writeresponsevalid was declared as writeresponsevalid_n.

    @sstrell : Thanks for your effort!

Schroeti's avatar
Schroeti
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

It is probably also important to mention that there are 2 clock domains within the memory mapped domain.

Here are the signal tap pictures of all hosts and agents. I have divided them into two different signal tap instances, since there are two different clocks. The SystemClock tap triggers the EmifClock tap.

For me it seems that there is no interference.

Schroeti's avatar
Schroeti
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Finally i found the bug. It was an error in the _hw.tcl script of the new custom agent: the writeresponsevalid was declared as writeresponsevalid_n.

@sstrell : Thanks for your effort!