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AChri1's avatar
AChri1
Icon for New Contributor rankNew Contributor
7 years ago

Platform Designer in Quartus 18.1 Standard gives the error: Error: max10_test_ddr3.mem_if_ddr3_emif_0: 'Debugging feature set' must be set to 'No Debugging' when 'Generate SOPC Builder compatible resets' is enabled.

I am trying to connect DDR3 memory with a 24bit data bus to an FPGA 10M40DAF484C7G to implement a 16bit data bus with ECC and via the FPGA connect it via a 32bit multiplexed data/address bus to an ex...
Abe's avatar
Abe
Icon for Frequent Contributor rankFrequent Contributor
7 years ago

Hi,

Can you share your design here so that we can take a look. Looks like you have to disable it in the Diagnostics tab of the EMIF controller or if you have any other diagnostic module the setting maybe in it.