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CAlex's avatar
CAlex
Icon for Contributor rankContributor
2 years ago
Solved

Platform designer error : subsystem ava mm bridge slave port

Hi, Ive made a subsystem into my main system: here is my sub system: The error is : Error: soc_system.subsystem_0.mm_bridge_0_s0: Interface must have an associated clock Reguards Al...
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  • ShengN_altera's avatar
    ShengN_altera
    2 years ago

    Hi,

    At Component Editor Signals & Interfaces tab, add Clock Output and Reset Output signals check screenshot below:

    Then modify the Clock Output and Reset Output Signals setting like below screenshot:

    Thanks,

    Best Regards,

    Sheng

sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
2 years ago

I think the issue is that with a pipeline bridge in a subsystem like this, you need to export both the agent interface (s0) and the clock interface of the bridge itself instead of going through the clock source component ("Custom Reset Synchronizer"?).

You say this is straight from the GHRD without any alterations? Try using a standard clock source component (or Clock Bridge component if this is Pro) instead of the "Custom Reset Synchronizer" which I've never seen before.

CAlex's avatar
CAlex
Icon for Contributor rankContributor
2 years ago

Hi

thank you for the reply,

the clock source IP works just fine,

the custom reset synchronizer is from GHRD of CycloneVsoc root/ip/custom_reset_synchronizer.

From the other Intel example (FPGA to SDRAM example mentioned in UG), the subsystem used the same way to connect and with no warning or error.

So I believe I must have not set it right.

Reguards

Alex