Forum Discussion

CAlex's avatar
CAlex
Icon for Contributor rankContributor
2 years ago
Solved

Platform designer error : subsystem ava mm bridge slave port

Hi, Ive made a subsystem into my main system: here is my sub system: The error is : Error: soc_system.subsystem_0.mm_bridge_0_s0: Interface must have an associated clock Reguards Al...
Platform
  • ShengN_altera's avatar
    ShengN_altera
    2 years ago

    Hi,

    At Component Editor Signals & Interfaces tab, add Clock Output and Reset Output signals check screenshot below:

    Then modify the Clock Output and Reset Output Signals setting like below screenshot:

    Thanks,

    Best Regards,

    Sheng

ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
2 years ago

Hi,


The Custom Reset Synchronizer is your custom IP? If replace Custom Reset Synchronizer with Clock Source Intel IP any difference?

If no more error means the problem at the Custom Reset Synchronizer.


Thanks,

Sheng


  • CAlex's avatar
    CAlex
    Icon for Contributor rankContributor
    2 years ago

    Hi

    yes you are right, the sync reset block is the problem of the issue,

    but it was not my IP, it is combined with the GHRD of CycloneVsoc.

    What this IP do to the clk is

    ```

    assign clk_out = clk_in;

    ```

    I dont understand why it will return such a error for my system.

    Reguard

    Alex