Platform Designer Components and terp file format

Thank you Wincent_Intel for taking the time to respond to my question. Unfortunately the link you provided does not provide the information I need to know to achieve what I want. Please bare in mind that I have read the documentation for PD before posting my question here, so it is unlikely that posting a link to the documentation is going to be of use.

To reiterate what I need help with:

I want to create a component that has parameter configurable number of Avalon ST sinks, between 1 and 4.

What does the HDL contain for this component? Do I create it with the signals for all 4 Avalon ST sink interfaces and have a parameter than tells PD (and the HDL) which ports are actually active?

An example of the relevant sections of the HDL and the _hw.tcl files showing how to do this would be very helpful!