Platform Designer - A10 PCIe SR-IOV Won't run at 8Gbps when SR-IOV is enabled.

FYI - I can't reliably get my solution to work. Seems that even with the DFE and lane reversal I still can't get to 5Gbps when we do a PCIe 'remove', FPGA-reprogram, and PCIe 'rescan' on the PCIe bus. I get 8Gbps "every" time when using the HC with just Avalon-ST selected (non-SR-IOV). Only from a system re-boot (SuperMicro) can I get 8Gbps, during the reboot the link is brought down (though no PCIe resets are generated). Seems to be an issue with resets related to PLLs loosing lock, and when I program the device the device is not running through the transceiver start-up/equalization process. Maybe there are subtle differences in the Avalon-ST and Avalon-ST SR-IOV implementations. The signal I/O is certainly different, and the way we collect configuration and status is different between the two. Maybe there is something else we are missing for generating app-reset and feedback to the HIP. Anyone else seeing these issues????