Forum Discussion

RWitt's avatar
RWitt
Icon for New Contributor rankNew Contributor
7 years ago

Platform Designer - A10 PCIe core - with SR-IOV not enabled and MSI-X enabled I can't export the msix signals.

(SR-IOV is "not" enabled) When I enable MSI-X support I can't get the conduit for those signals to show up in Platform Designer, only the MSI signals. I enabled that support but nothing is generated ...
RWitt's avatar
RWitt
Icon for New Contributor rankNew Contributor
7 years ago

Yes, I figured that out last night; for the Avalon-ST without SR-IOV the MSI-X interrupts need to be generated on the ST interface, not the convenient MSI-X signals the SR-IOV version supports (a pain having to have `ifdef(s) to change functionality and pinout, though I'll just resign myself to not using that MSI-X interface on the SR-IOV version and just using write-TLPs). As the Intel documentation says "The Application Layer transmits MSI-X interrupts on the Avalon-ST TX interface. MSI-X interrupts are single dword Memory Write TLPs".

Thanks.

Consider this issue closed.