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For instance, a generic pipeline stage a component, that given a function with some input and some output, builds a component, with registers at the back to wait for the next stage of the pipe, and signals ready_to_receive, and so on.
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But you can just about do this with packages at the moment. Just have the "function" declared in a package, and the package body decalred in another file. Then when synthesising the files, just select the correct package that implements the appropriate function. Or just use generics to use the appropriate function. 2008 does not solve any real problems.
System verilog does not have generic types, because types in SV are rather fluid (like C). You can cast just about anything to just about anything else easily. The OO parts of SV help control that a bit, but there is no chance any of the object orientation will ever be supported by quartus, mainly because it's for verification.
You can do anything you want to do in VHDL 1993.
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