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What "high level language" features do you want? there is nothing that cannot be done with VHDL 1993. Most VHDL 2008 features are there really to catch up in a simulation space when compared to SV. Quartus already supports the more useful features of 2008, the features you are suggesting dont really add any value to synthesis.
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For instance, a generic pipeline stage a component, that given a function with some input and some output, builds a component, with registers at the back to wait for the next stage of the pipe, and signals ready_to_receive, and so on.
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