Plans to support VHDL 2008?

This is only a question Altera can answer (and they dont post in their own forums).

But Xilinx also do not support generic type parameters and functions either. (and their 2008 support is currently better than Altera's).

I suspect it wont come along until some big customers insist on it (which will probably never happen).

To be honest - most people are now moving SV for synthesis instead (like altera). it makes sense when all your verification will be in SV/UVM anyway.

What is Sv?

Thanks

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This is only a question Altera can answer (and they dont post in their own forums).

But Xilinx also do not support generic type parameters and functions either. (and their 2008 support is currently better than Altera's).

I suspect it wont come along until some big customers insist on it (which will probably never happen).

To be honest - most people are now moving SV for synthesis instead (like altera). it makes sense when all your verification will be in SV/UVM anyway.

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Thanks for the clarification. This definitively looks like it is the case.

If someone from Altera is reading, why not placing a suggestion in the Quartus II manual? Something like, in the page about Verilog 2008 support "We suggest users to use System Verilog for high level language features".

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Thanks for the clarification. This definitively looks like it is the case.

If someone from Altera is reading, why not placing a suggestion in the Quartus II manual? Something like, in the page about Verilog 2008 support "We suggest users to use System Verilog for high level language features".

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What "high level language" features do you want? there is nothing that cannot be done with VHDL 1993. Most VHDL 2008 features are there really to catch up in a simulation space when compared to SV. Quartus already supports the more useful features of 2008, the features you are suggesting dont really add any value to synthesis.

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What "high level language" features do you want? there is nothing that cannot be done with VHDL 1993. Most VHDL 2008 features are there really to catch up in a simulation space when compared to SV. Quartus already supports the more useful features of 2008, the features you are suggesting dont really add any value to synthesis.

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For instance, a generic pipeline stage a component, that given a function with some input and some output, builds a component, with registers at the back to wait for the next stage of the pipe, and signals ready_to_receive, and so on.

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For instance, a generic pipeline stage a component, that given a function with some input and some output, builds a component, with registers at the back to wait for the next stage of the pipe, and signals ready_to_receive, and so on.

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But you can just about do this with packages at the moment. Just have the "function" declared in a package, and the package body decalred in another file. Then when synthesising the files, just select the correct package that implements the appropriate function. Or just use generics to use the appropriate function. 2008 does not solve any real problems.

System verilog does not have generic types, because types in SV are rather fluid (like C). You can cast just about anything to just about anything else easily. The OO parts of SV help control that a bit, but there is no chance any of the object orientation will ever be supported by quartus, mainly because it's for verification.

You can do anything you want to do in VHDL 1993.

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For instance, a generic pipeline stage a component, that given a function with some input and some output, builds a component, with registers at the back to wait for the next stage of the pipe, and signals ready_to_receive, and so on.

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Out of curiosity: could you elaborate a bit more? Perhaps show a block diagram?