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jjxichn's avatar
jjxichn
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10 months ago

Plan Stage Taking more time than expectation

Hello All, I am using Quartus 22.4 to do place and route to generate bitstream. I found one design taking about 75% of total area is using 15 hours on the plan stage while other design using similar...
Hdl
RichardT_altera's avatar
RichardT_altera
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10 months ago

Your understanding is correct, the Plan stages—places all periphery elements (such as I/Os and PLLs) and determines a legal clock plan, without core placement or routing.

With 15 hours on Plan Stage, something might have gone wrong with your design. Even 2-3 hours is consider long. Try to isolate your design by uncomment the instantiation of the design modules or removing portions of RTL code.

If the time reduces significantly, this might indicates that the issue lies within the commented-out portion of the design.

Perhaps you may check the what are the differences between these two designs (15 hrs vs 2/3 hrs) that might indicate so. Different IP usage, design constraints, etc.

Alternatively, you may opt to upgrade your design to the latest Quartus version and see if the time improves.

Regards,

Richard Tan