jjxichn
New Contributor
10 months agoPlan Stage Taking more time than expectation
Hello All,
I am using Quartus 22.4 to do place and route to generate bitstream. I found one design taking about 75% of total area is using 15 hours on the plan stage while other design using similar area only spends 2-3 hours on the plan stage. So I am wondering are there any ways to reduce the time consumed on plan stage? I learned that the plan stage is doing device periphery placement and routing and the device are identical among these projects.