Hi Richard,
I’m very sorry for the delay. I was busy with several other tasks and had to shift the task regarding the GPIO error.
I was able to reproduce the error in a small test design.
I’d like to ask if you could have a look into the error I’m getting during plan phase and if there is a possibility to resolve it.
Short summary:
I’m trying to create 5 GPIOs in the same IO bank (3V). Two of them are used as bidirectional IO and three are output only.
Quartus is generating the ‘quartus_inserted_3vio_obuf_oe_wirelut’ which results in an error.
In Quartus 20.4 this wasn’t an issue but with 22.4 I got the AIB_3VIO_OE error.
If you need any further information do not hesitate to contact me.
Kind regards,
Michael
Occasional Contributor
