Forum Discussion

Occasional Contributor

2 years ago

Plan error after upgrading Quartus Pro version 20.4 to 22.4

Hi, I just upgrade my project for a Stratix 10 MX FPGA from 20.4 to 22.4. With 20.4 the design run was successful but after upgrading to 22.4 I see planning errors with the same RTL / IP set: ...

ltc2226_clk_output_gpio.ip.zip3 KB

i2c_sda_gpio.ip.zip3 KB

i2c_scl_gpio.ip.zip3 KB

Compilation

RichardT_altera

Super Contributor

2 years ago

Could you please share your .qar design file by archiving the project (Project > Archive Project) instead of providing three individual IP files?

This will allow me to duplicate the error in order to debug the issue effectively.

Regards,

Richard Tan

Forum Discussion

Plan error after upgrading Quartus Pro version 20.4 to 22.4

Recent Discussions

Duplicate_hierarchy_depth / duplicate_register

Timing analysis - long combinational path

Automatically added negative node for TDS output doesn't work with Agilex 5

Quartus 20.1std compilation fails for Quartus map - Device 10AS057K2F40I1SG

QuartusPro 25.3 Crashed after using the Signal Tap Logic Analyzer