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AGaru1's avatar
AGaru1
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

PCIe HARD IP +

Hi, i'm trying to run a synthesis of my Design for Stratix 10 on Quartus Pro 19.4. In my TOP ENTITY i added the PCIe HARD IP + and connected it to my entities. I've updated the .qsf file with the...
AGaru1's avatar
AGaru1
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Hi!

I integrated the Pcie Hard IP.

The VHDL generated code has problems.

I generated the IP TOP in verilog and the synth went well!!

THank you!

  • BoonT_Intel's avatar
    BoonT_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    6 years ago

    I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.