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AGaru1's avatar
AGaru1
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

PCIe HARD IP +

Hi, i'm trying to run a synthesis of my Design for Stratix 10 on Quartus Pro 19.4. In my TOP ENTITY i added the PCIe HARD IP + and connected it to my entities. I've updated the .qsf file with the...
BoonT_Intel's avatar
BoonT_Intel
Icon for Frequent Contributor rankFrequent Contributor
5 years ago

Hi Sir,

I am so sorry, I just found that this is VHDL code which I am not familiar with it. Thus, I will need your design QAR file to use quartus compile and replicate the error to understand the problem.

If you can't give me the full design, then you can simplify it by remove out the other unrelated component and remain the PCIe IP that able to demonstrate the error.

Thanks.