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AGaru1's avatar
AGaru1
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

PCIe HARD IP +

Hi, i'm trying to run a synthesis of my Design for Stratix 10 on Quartus Pro 19.4. In my TOP ENTITY i added the PCIe HARD IP + and connected it to my entities. I've updated the .qsf file with the...
AGaru1's avatar
AGaru1
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Hi,

thank you for your reply.

The TOP of the PCIe generated by Quartus shows a port with 4 bits : intx_req_i : in std_logic_vector(3 downto 0)