Forum Discussion
AGaru1
Occasional Contributor
Occasional ContributorPCIe HARD IP +
Hi, i'm trying to run a synthesis of my Design for Stratix 10 on Quartus Pro 19.4. In my TOP ENTITY i added the PCIe HARD IP + and connected it to my entities. I've updated the .qsf file with the...
BoonT_Intel
Frequent Contributor
Frequent ContributorHi Sir,
This is an synthesis error, it is not related with the QSF assignment.
From the error message, it seem like you are not connecting the intx_req_i correctly from yuor top level. This port is a 9 bits bus but you define it as 4 bit in your top level.
