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Altera_Forum's avatar
Altera_Forum
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14 years ago

PCIe BFM

So Altera have decided to stop shipping the PCI BFM with their IP, meaning their simulation demos are now a bit useless:

# ** Failure: SUCCESS: BFM model not available!

So the reply from mysupport was:

"the error that you are seeing is not because you have done anything wrong, or that you are using vhdl rather than verilog as your simulation environment. unfortunately i have been instructed to report that due to business concerns, altera is not currently shipping a pci express bus functional model in the current version of the tools. i'm afraid that there is not anything that i am able to do to assist you in generating a pci express bfm for this version.

in order to simulate interactivity with the pci express core, you will need to source a pci express bus functional model to plug into the testbench."

So does anyone know where I can get a PCI BFM model from that will work with this demo, or what was the last version of Quartus to ship with the BFMs?

12 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Chapter 2 of "ug_c5_pcie_avmm.pdf" document has the details simulation steps for endpoint core. You can try configure the core to rootport and use the same simulation method see how it goes.

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    You can get the BFM only from Q11.0

    After Q11.0sp1, the BFN was no longer provided from Altera
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Tricky,

    When you generate the PCIe core using MegaWizard, all the testbench files including the BFM are also generated. For example, if you generate a core called "pcie_core", then the BFM will be in the location similar to.

    ..\pcie_core\pcie_core_examples\chaining_dma

    Have you tried that?

    --- Quote Start ---

    So Altera have decided to stop shipping the PCI BFM with their IP, meaning their simulation demos are now a bit useless:

    # ** Failure: SUCCESS: BFM model not available!

    So the reply from mysupport was:

    "the error that you are seeing is not because you have done anything wrong, or that you are using vhdl rather than verilog as your simulation environment. unfortunately i have been instructed to report that due to business concerns, altera is not currently shipping a pci express bus functional model in the current version of the tools. i'm afraid that there is not anything that i am able to do to assist you in generating a pci express bfm for this version.

    in order to simulate interactivity with the pci express core, you will need to source a pci express bus functional model to plug into the testbench."

    So does anyone know where I can get a PCI BFM model from that will work with this demo, or what was the last version of Quartus to ship with the BFMs?

    --- Quote End ---

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    For version 11 and 11.1, Altera have stopped providing the BFM. They should be providing it again in 12.0

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    It is pretty easy to get the BFM from v11.0 working in v11.0SP1. At least in our setup, there are only one or two files you need to get from v11.0 and overwrite in v11.0SP1. They are located in pcie_examples/common/testbench and are altpcietb_bfm_rpvar_64b_x8_gen1_pipen1b.vo and possibly altpcietb_bfm_rpvar_64b_x8_gen2_pipen1b.vo for a gen2 config. We are seeing some errors reported with Txelecidle with this setup, but it appears to recover and work just fine.

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    I've found that the BFM provided by one of Altera's distributors (Macnica) is the easiest to use (it's designed specifically for Altera FPGAs). The free version always ends up downtraining to Gen1x1, but the little "installer" that comes with it uses the demo/example designs (so if you have Gen2x2, it'll work, but you'll only get Gen1x1 rates until you pay). You have to use Quartus 12.0 or newer, though (they have versions that work with older Quartus tools, but you'd have to contact them).

    You can also get a "simple design example" from them, which I found much more useful than the chaining DMA stuff because it's intuitive (they separate the design from the testbench and do simple reads/writes) -- good for getting started. Everything is script driven, so you can do complex things or just do simple read/write stuff like "read <address>" / "write <addresss>, <data>."

    They call it "DrivExpress". The free version often does what you want, but they'll work with you on the price if you need to sim lots of data/throughput. Google "DrivExpress" and it should show up near the top.
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Hi,

    I am going to use PCIe Avalone MM hard IP in Cyclone V device. Parameter settings are such that gen-1, x1, root port, 125Mhz, multiple MSI (8). CRA port is connected to HPS. Root port is connected to MSI to GIC IP vector port. HSP avalon master is connected to MSI to GIC IP CSR port. Now I want to generate interrupt request by root port to MSI to GIC through TLP serial interface. I am referring "ug_c5_pcie_avmm.pdf" document for simulation steps. I didnt find any ready made end point BFM which is directely connected to root port PCI express link for TLP interface. so kindly suggest me about simulation model for TLP generation to my root port design.

    Thanks

    Dipen