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Altera_Forum
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14 years ago

PCIe BFM

So Altera have decided to stop shipping the PCI BFM with their IP, meaning their simulation demos are now a bit useless: # ** Failure: SUCCESS: BFM model not available! So the reply from mys...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Hi,

I am going to use PCIe Avalone MM hard IP in Cyclone V device. Parameter settings are such that gen-1, x1, root port, 125Mhz, multiple MSI (8). CRA port is connected to HPS. Root port is connected to MSI to GIC IP vector port. HSP avalon master is connected to MSI to GIC IP CSR port. Now I want to generate interrupt request by root port to MSI to GIC through TLP serial interface. I am referring "ug_c5_pcie_avmm.pdf" document for simulation steps. I didnt find any ready made end point BFM which is directely connected to root port PCI express link for TLP interface. so kindly suggest me about simulation model for TLP generation to my root port design.

Thanks

Dipen