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JWrig25's avatar
JWrig25
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6 years ago

PCI Express Avalon-MM High-Performance DMA Reference Design for Stratix V does not compile.

The compilation of the PCI Express Avalon-MM High-Performance DMA Reference Design for Stratix V fails in Quartus Prime Standard Edition 18.1. The errors say that the IP components need to be upgraded. I have tried to upgrade the top.qsys in the Platform Designer but when I click the Generate HDL, the generation finishes with errors when I include synthesis and finishes with warnings if I leave it out. Which ever I choose however, the resulting compilation fails and tells me some IP components still need to be upgraded. I do not know what to do, all my attempts to get this design to compile have not worked.

8 Replies

  • BoonT_Intel's avatar
    BoonT_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    6 years ago

    What is the original quartus version of the design? Maybe you can use the original quartus version (without upgrade) and compile.

    • JWrig25's avatar
      JWrig25
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      6 years ago

      The design says for Stratix V use quartus 15.1 or newer, I guess I'll try 15.1​

  • BoonT_Intel's avatar
    BoonT_Intel
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    6 years ago

    is it a QAR or a zip file? If zip, you can open the QSF file and check the version used.

    If QAR, once you able to open with quartus, you also can open the QSF to check.

    • JWrig25's avatar
      JWrig25
      Icon for Occasional Contributor rankOccasional Contributor
      6 years ago

      The Avalon-MM design file is a .QAR zip file.

    • JWrig25's avatar
      JWrig25
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      6 years ago

      The .QSF file says the original Quartus version is 18.1.0 which is the version that I have installed. I have no idea why the design does not work, the software is the right version but the design fails to compile and says that the IP needs to be updated which also fails. Additionally, I tried a different IP design for Stratix V and that one also failed to compile, because the design was "too big for the FPGA" and used too many pins. Both of these designs are specific for my FPGA and my software but nothing actually works. Please help.

  • BoonT_Intel's avatar
    BoonT_Intel
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    6 years ago

    This design should create with old quartus version. Looks like it is create with QII 13.0 with some patches. I just use 14.0 and I can open it correct and compile successful.