Pb with shifting

architecture behave of convo is
signal rg: std_logic_vector(1 downto 0):="00";
signal c1: std_logic_vector(31 downto 0);
signal c2: std_logic_vector(31 downto 0);
begin
process(clk)
begin
if (clk 'event and clk='1') then
for i in 0 to 31 loop 
c1(i)<=wr_data(i) xor rg(1);
rg(1)<=rg(0);        :confused:
rg(0)<=wr_data(i);  :confused:
end loop;
end if;
end process;
C1_out<=c1;
--C2_out<=c2;
end;

Hello mates, I am having problem with my code : the instructions" rg(1)<=rg(0); and rg(0)<=wr_data(i); " seems that they r not working

I start my waveform(with no error in synth) and the result show that it is keep doing c1(i)<=wr_data(i) xor rg(1); for the initial rg(1) !!!

What could be the problem ? is it code syntax or what ?!