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Altera_Forum
Honored Contributor
Honored ContributorPb with shifting
architecture behave of convo is
signal rg: std_logic_vector(1 downto 0):="00";
signal c1: std_logic_vector(31 downto 0);
signal c2: std_logic_vector(31 downto 0);
begin
process(clk)
begin
if (clk '...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- rg(0) is always assigned to wr_data(31), because signals take the last value assigned to them. did you mean for rg to be a variable? --- Quote End --- Yes I need rg(0) to be assigned to wr_data(i) ( same for assigning rg(1)) as you said rg should be variable every iteration
